1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, in particular to a semiconductor device with capacitor electrodes and a manufacturing method thereof.
2. Description of the Background Art
Conventionally a DRAM (Dynamic Random Access Memory) as one of the semiconductor devices is known. FIG. 9 is a schematic cross section view showing a semiconductor device according to a prior art. The semiconductor device according to a prior art is described with reference to FIG. 9.
Referring to FIG. 9, the semiconductor device is a DRAM which includes a field effect transistor and a capacitor formed on a semiconductor substrate 101. The capacitor stores an electric charge as a memory signal. And the field effect transistor works as a switching element which controls the storage of the electric charge to the capacitor. Conductive regions 102a to 102e are formed in the main surface of the semiconductor substrate 101 with gaps between the regions. The conductive regions 102a to 102d become source and drain regions of the field effect transistors. A gate insulating film 103a to 103c is formed on the semiconductor substrate 101 above the channel regions located between the conductive regions 102a to 102d. Gate electrodes 104a to 104c are formed on the gate insulating film 103a to 103c. A side wall insulating film 105a to 105f is formed on the side walls of the gate electrodes 104a to 104c. A coating insulating film 106a to 106c is formed on the gate electrodes 104a to 104c. A field effect transistor is formed of the gate electrode 104a, the gate insulating film 103a and conductive regions 102a and 102b as the source and drain regions, respectively. Another field effect transistor is formed of the gate electrode 104b, the gate insulating film 103b and the conductive regions 102b and 102c as the source and drain regions, respectively. Still another field effect transistor is formed of the gate electrode 104c, the gate insulating film 103c and the conductive regions 102c and 102d as the source and drain regions, respectively.
The first interlayer insulating film 107 is formed on the coating insulating film 106a to 106c, the side wall insulating film 105a to 105f and the main surface of the semiconductor substrate 101. Contact holes 108a and 108b are formed in the regions located above the conductive regions 102b and 102c in the first interlayer insulating film 107. Conductive material film 109a and 109b, such as a doped polysilicon film, is filled in inside the contact holes 108a and 108b. The second interlayer insulating film 110 is formed on the first interlayer insulating film 107. A contact hole 111a is formed in the second interlayer insulating film 110 in the regions located above the conductive material film 109b. In addition, a contact hole 111b is formed in the region located above the conductive region 102e in the main surface of the semiconductor substrate 101 by removing part of the first and the second interlayer insulating films 107 and 110. A conductive material film 115a and 115b, such as a tungsten film, is filled in inside of the contact holes 111a and 111b, respectively. The first wiring layers 112a and 112b are formed on the conductive material film 115a and 115b, respectively.
The third interlayer insulating film 113 is formed on the first wiring layer 112a and 112b and the second interlayer insulating film 110. A contact hole 114 is formed in the reference located above the conductive material film 109a by removing part of the second and of the third interlayer insulating films 110 and 113. A conductive material film 116 is filled in inside of the contact hole 114.
The fourth interlayer insulating film 117 is formed on the third interlayer insulating film 113. A contact hole 150 is formed in the region located above the first wiring layer 112b by removing part of the third and the fourth interlayer insulating films 113 and 117. A conductive material film 151 is filled in inside of the contact hole 150.
The fifth interlayer insulating film 118 is formed on the fourth interlayer insulating film 117. An aperture part 119 is formed in the regions located above the conductive material film 116 by removing part of the fourth and the fifth interlayer insulating film 117 and 118. A capacitor lower electrode 120 which is connected to the conductive material film 116 is formed inside of the aperture part 119. A dielectric film 121 is formed so as to extend from the capacitor lower electrode 120 to the upper surface of the fifth interlayer insulating film 118. A capacitor upper electrode 122 is formed on the dielectric film 121 so as to fill in the inside of the aperture part 119 and to extend over the upper surface of the fifth interlayer insulating film 118. A capacitor is formed of the capacitor lower electrode 120, the dielectric film 121 and the capacitor upper electrode 122.
The sixth interlayer insulating film 123 is formed on the capacitor upper electrode 122 and the fifth interlayer insulating film 118. A contact hole 152a is formed in the region located above the capacitor upper electrode 122 of the sixth interlayer insulating film 123. A contact hole 152b is formed in the region located above the conductive material film 151 by removing part of the fifth and the sixth interlayer insulating films 118 and 123. A conductive material film 153a and 153b, such as a tungsten film, is filled in inside of the contact holes 152a and 152b. The conductive material film 153a is connected to the capacitor upper electrode 122. The conductive material film 153b is connected to the conductive material film 151. The second wiling layer 154a and 154b, made of aluminum or the like, is formed on the conductive material film 152a and 152b. The second wiring layer 154a is utilized to fix the potential of the capacitor upper electrode 122. In a semiconductor device such as a DRAM, as shown in FIG. 9, a plurality of memory cells with capacitors are arranged in a matrix form on the substrate 101. Then, an interlayer insulating film (not shown) is formed on the second wiring layer 154a and 154b. 
As for semiconductor devices as represented by DRAM the demand for miniaturization and high levels of integration continues to grow strongly. Therefore, the size of a memory cell of a DRAM as shown in FIG. 9 is becoming smaller and smaller. However, it is necessary to store a specific amount of electric charge in a capacitor which stores an electric charge in a memory cell. Therefore, capacitor structures which are in the form of extending in the vertical direction, such as a cylindrical type capacitor as shown in the figures or a thick film type capacitor, have been adopted for the purpose of securing the capacitance of the capacitors while making the size of the memory cells smaller. On the other hand, it is necessary to connect the first wiring 112b, which is connected to the conductive region 102e, with the second wiring layer 154b via the contact holes 152b and 150 for the purpose of supplying a signal to, or of fixing the potential of, the conductive region 102e, or the like, which is located below the capacitor upper electrode 122. At this time, the contact hole 152a, located above the capacitor upper electrode 122, and the contact hole 152b, located below the second wiring layer 154b, have different depths due to the structure of the capacitor. Thereby, in the case that those contact holes 152a and 152b are formed in one etching step, it is necessary to continue the etching until the contact hole 152b achieves a predetermined depth. At this time, the capacitor upper electrode 122 undergoes excessive etching at the bottom of the contact hole 152a. As a result of this, the problem arises that the capacitor upper electrode 122 receives damage or the contact hole 152a penetrates the capacitor upper electrode 122. Therefore, conventionally the etching step of forming the contact hole 152a and the etching step of forming the contact hole 152b are carried out separately. As a result of this, the number of steps for a process of the semiconductor device has increased and this becomes the cause of increased manufacturing cost of a semiconductor device.
In addition, overlapping mask errors in the lithography process for forming the second wiring layer 154a and 154b and the lithography process for forming contact holes 152a and 152b make the positions of the second wiring layer 154a and 154b and the contact holes 152a and 152b shift. In this case, the second wiling layer 154a and the capacitor upper electrode 122 are not connected and, therefore, defects occur in the semiconductor device.
In addition, together with the miniaturization of semiconductor devices the wiring width, the wiring height (section area of the wiring) and the gap between wires of the second wiring layer 154a and 154b need to be made smaller. However, as the section area of wires becomes smaller in this way the wire resistance of the second wiring layer 154a and 154b increases. Such an increase of the wire resistance leads to a wiring delay. As a result of this some necessary characteristics, such as operational speed, fail to be achieved in the semiconductor device and, in some cases, defects nonetheless occur.
The purpose of the present invention is to provide a semiconductor device and a process for the same wherein it is possible to prevent the occurrence of defects and to reduce the manufacturing cost.
A semiconductor device according to one aspect of this invention includes capacitor electrodes, an insulating film and a wiring layer. Capacitor electrodes are formed on the semiconductor substrate. The insulating film, formed on the capacitor electrodes, has trenches, which expose parts of the capacitor electrodes, and an upper surface. The wiring layer is filled in inside of the trenches, has an upper surface and is connected to the capacitor electrodes. The upper surface of the wiring layer is located on approximately the same plane as the upper surface of the insulating film.
In this way, the wires connected to the capacitor electrodes can be in a so-called damascene wiring structure and, therefore, the process for the semiconductor device can be simplified to a greater degree than in the prior art.
In addition, conventionally the capacitor electrodes and a wiring layer, made of aluminum or the like, are connected via a conductive material film, such as tungsten plugs, formed inside of the contact holes. Therefore, the connection interface between the wiring layer and the conductive material film becomes a connection interface between different types of materials, which enhances the interface resistance, or the like, and, therefore, the resistance against electromigration has been reduced. In the present invention, however, the wiring layer is of the damascene wiring structure while parts of the capacitor electrodes are exposed in the trenches so that the lower surface of the wiring layer is in the state directly connected to the capacitor electrodes. Therefore, it is not necessary to form tungsten plugs. Therefore, the resistance against electromigration of the wiring layer can be prevented from becoming reduced.
In addition, by forming trenches in the insulating film and by filling in the inside of the trenches with a conductive material film, the formation of the wiring layer and the contact of the wiring layer with the capacitor electrodes can be implemented at the same time and, therefore, no problem occurs wherein the contact holes and the wiring layer, which is supposed to be formed above these contact holes, become shifted in position, as in the prior art. Accordingly, the occurrence of defects due to such a position shift can be prevented.
In addition, since the upper surface of the wiring layer and the upper surface of the insulating film are located approximately on the same plane, no step exists due to this wiring layer on the upper surface of this wiring layer. Therefore, in the case that another insulating film, or the like, is formed on the insulating film, no step is formed on the upper surface of that other insulating film due to the steps on the upper surface of the wiring layer. Accordingly, in the case that an upper layer wiring layer, or the like, is formed on that other insulating film, defects such as a discontinuity of the upper layer wiring layer due to the above described steps can be prevented from occurring.
In addition, there are cases where another wiring layer formed in the same layer as the wiring layer and the above described conductive region are connected for the purpose of supplying a signal to a conductive region located below the capacitor electrodes. At this time, in a region which is not overlapped with the capacitor electrodes in the same plane, it is necessary to form another contact hole which reaches the above described conductive region, a conductive material film which is filled in inside of that other contact hole and another wiring layer connected to the conductive material film in the insulating film. On the other hand, conventionally a contact hole is formed for the connection between the capacitor electrodes and the wiring layer. Then, since this contact hole and the above described other contact hole have different depths, it is necessary to form them in separate etching steps, respectively. This is because the semiconductor device is miniaturized so as to have a structure where the capacitors extend in the vertical direction and the difference of the depths between the contact hole and the above described other contact bole becomes, increasingly, larger. In the present invention, however, no contact hole is formed on the capacitor electrodes and the lower surface of the wiring layer directly contacts the capacitor electrodes. That is to say, even when the semiconductor device is miniaturized it is not necessary to form a plurality of contact holes of which the depths are different, as in a prior art and, therefore, the manufacturing process of the semiconductor device can be further simplified.
The semiconductor device, according to the above described one aspect of the present invention, may include conductive regions located below the insulating film. It is preferable that contact holes which reach to the conductive regions and the other trenches which are connected to these contact holes are formed in the insulating film. Moreover, the semiconductor device according to the above described one aspect of the present invention, preferably, includes another wiring layer which is filled in inside of the other trenches and the contact holes.
In this case, the other wiring layer formed in the insulating film can be formed in a so-called dual damascene process wherein the inside of the contact holes and the inside of the other trenches are filled in with a conductive material film. Then, as described in the manufacturing process below, the other trenches wherein the above described other wiring layer is located and the trenches where the wiring layer is located are formed in the same etching step so that, in the case that the other wiring layer is formed as described above, the increase in the number of manufacturing steps can be limited to the minimum. Therefore, the increase of the manufacturing cost of the semiconductor device can be held down.
In the semiconductor device according to the above described one aspect of the present invention, the trenches and the other trenches of the insulating film may be formed so as to extend, approximately, in parallel.
In this case, the first wiring layer which contacts the lower surface of the capacitor electrodes can be formed so as to extend parallel the second wiring layer. Accordingly, the contact area between the capacitor electrodes and the wiring layer can be increased and, therefore, the electric contact between the capacitor electrodes and the wiring layer can be made more failure proof.
In the semiconductor device according to the above described one aspect of the present invention, the trenches of the insulating film may include a plurality of aperture parts.
In this case, the contact area between the wiring layer and the capacitor electrodes can be arbitrarily changed by changing the areas of bottoms of the aperture parts. As a result of this, the electric resistance value between the wiring layer and the capacitor electrodes can be arbitrarily changed.
In addition, in the case that the trenches include a plurality of aperture parts in this way and the wiring layer is formed inside of the aperture parts, respectively, an upper layer wiring layer which is located above the wiring layer, may be formed so as to make a connection between respective wiring layer formed inside of the aperture layers.
In the semiconductor device according to the above described one aspect of the present invention, it is preferable that the wiring layer includes copper.
In this case, copper has a lower electrical resistance value than aluminum, which is conventionally used as a material for the wiring layer. Accordingly, in the case that copper is used for the material for the wiring layer the wiring resistance can be reduced more than in the prior art. Therefore, the occurrence of the wiring delay can be prevented.
In the semiconductor device according to the above described one aspect of the present invention, it is preferable that a barrier metal layer is formed on the inside walls of said trenches.
In this case, the barrier metal layer can prevent materials, such as copper, which form the wiring layer from defusing into the insulating film or the capacitor electrodes.
In a method of manufacturing a semiconductor device according to another aspect of the present invention, capacitor electrodes are formed on a semiconductor substrate. An insulating film which has an upper surface is formed on the capacitor electrodes. In the insulating film trenches are formed so as to expose parts of the capacitor electrodes. A conductive material film is formed so as to fill in inside of the trenches and to extend to the upper surface of the insulating film. By removing the conductive material film which is located on the upper surface of the insulating film and by removing parts of the conductive material film which is located on the surface of the trenches in the insulating film, a wiring layer which is made of the conductive material film which fills in inside of the trenches and has an upper surface which is located on, approximately, the same plane as the upper surface of the insulating film is formed.
Here, in a process for a wiring layer which is connected to the capacitor electrodes according to a prior art, the step of forming contact holes in the insulating film, the step of forming a conductive material film inside of the contact holes, the step of removing extra conductive material film located on the upper surface of the insulating film, the step of forming a conductive material film which becomes a wiring layer on the surface of the contact holes and the step of forming a wiring layer by partially removing this conductive material film through etching using a resist film as a mask and carried out. That is to say, according to the process for a semiconductor device in a prior art, the etching steps and the film formation steps are carried out twice, respectively. In the present invention, however, by making the wiring layer electrically connected to the capacitor electrodes have a so-called damascene wiring structure, the step of forming trenches in the insulating film, the step of forming a conductive material film which becomes the wiring layer inside of those trenches and the subsequent step of removing the conductive material film located on the upper surface of the insulating film using a chemical mechanical polishing method (CMP method), or the like, which make up a fewer number of steps than in a prior art, can, together, form the wiring layer. As a result of this, the process for a semiconductor device can be simplified. And by following these steps the semiconductor device according to the present invention can be easily manufactured.
In the method of manufacturing a semiconductor device according to above described other aspect of the present invention, conductive regions located beneath the insulating film may be formed and contact holes which reach to the conductive regions may be formed in the insulating film. The step of forming trenches may include the formation of the other trenches in the regions located above the contact holes of the insulating film. The step of forming the conductive material film may include the formation of a conductive material film which becomes the other wiring layer so as to fill in the inside of the contact holes and the other trenches.
In this case, the step of forming the other trenches located above the contact holes and the step of forming trenches which reach to the capacitor electrodes can be carried out simultaneously. Then, since the wiring layer formed inside of the trenches is directly connected to the capacitor electrodes, it is not necessary to form contact holes into which tungsten plugs, or the like, are filled in separately from the wiring layer on the capacitor electrodes as in the prior art. Therefore, the process for a semiconductor device can be simplified to a greater degree than in a prior art.
In addition, in the case that the depth of the trenches and the other trenches which are formed in one etching step in the insulating film is set at approximately the same distance from the upper surface of the insulating film to the upper surface of capacitor electrodes, excessive etching of the capacitor electrodes at the bottoms of the trenches can be prevented in this etching step. Therefore, the capacitor electrodes can be prevented from undergoing damage through excessive etching.
In the method of manufacturing a semiconductor device according to the above described other aspect of the present invention, the step of forming trenches may include the formation of trenches which extend approximately parallel to the other trenches.
In this case, the one wiring layer which extends in parallel to the other wiring layer and of which the lower surface contacts the upper surface of the capacitor electrodes can be formed. Accordingly, the contact area between the capacitor electrodes and the wiring layer can be increased. As a result of this, the electric connection between the capacitor electrodes and the wiring layer can be made without fail.
In the method of manufacturing a semiconductor device according to the above described other aspect of the present invention, the step of forming trenches may include the formation of a plurality of aperture parts in the insulating film so as to expose parts of the capacitor electrodes.
In this case, by changing the area of the bottoms of the aperture parts the contact area between the wiring layer and the capacitor electrodes can be arbitrarily changed.
In the method of manufacturing a semiconductor device according to the above described other aspect of the present invention, it is preferable for the conductive material film to include copper.
In this case, as a material of the wiring layer copper, of which the electric resistance value is lower than aluminum which is conventionally used, can be used for the wiring layer.